The present embodiments relate to selectively blocking branch instruction prediction, and more particularly to providing an instruction within a stream of instructions to be executed to block branch prediction of a predetermined number of future branch instructions.
Processors use pipelines to increase the speed with which an instruction stream may be processed. The pipeline may have a number of processing stages, and as one instruction is processed in one stage, a next instruction may be processed in an upstream stage. When the stream of instructions includes a branch instruction, the processor may need to execute the branch instruction, or run the branch instruction through the whole pipeline, to determine a next instruction to execute. To increase efficiency, processors may determine when the instruction stream includes a branch instruction and may predict which instruction should follow the branch instruction in the pipeline.
However, incorrect predictions by the processor may result in decreased processing efficiency. For example, if the processor predicts a next instruction to follow a conditional branch instruction, but the branch is not taken, then the next instruction and any subsequent instructions that have been processed at various stages of the pipeline must be cleared, and new instructions from the original stream including the branch instruction must be provided at the start of the pipeline. As a result, upstream stages of the pipeline may stand idle for multiple cycles following an incorrect branch prediction.